I. Field of the Disclosure
The technology of the disclosure relates generally to computer memory, and more specifically to pre-charging bitlines of static random access memory (SRAM) for memory accesses.
II. Background
A memory cell is a basic building block of computer data storage, also known as “memory.” A computer system may either read data from or write data to memory, of which there are different types. For example, one type of memory is static random access memory (SRAM). As an example, SRAM may be used as cache memory in a central processing unit (CPU) system. A SRAM cache may be comprised of a tag array and a data array. The tag array contains indexes to memory addresses stored in a SRAM data array. The tag array receives a memory address as part of a memory access request from a CPU. The tag array uses the memory address to determine if the SRAM data array contains valid data for the memory address in the memory access request. If valid data exists, the data can be directly accessed from the SRAM data array as opposed to being accessed from a higher level memory, such as a higher level cache memory or main memory.
SRAM data arrays are organized in rows and columns of SRAM bitcells. The SRAM bitcells are each capable of storing a single bit of information. A memory access request to a SRAM data array typically involves selecting an entire row of SRAM bitcells to access bits stored in each column of the selected row. In this regard, FIG. 1 illustrates an example of a standard six transistor (6-T) SRAM bitcell 10 as a SRAM cell that may be provided in a SRAM to store a single bit of information 12. The single bit of information 12 is stored in two (2) cross-coupled inverters 14, 16 in the 6-T SRAM bitcell 10. The 6-T SRAM bitcell 10 has two stable states that are used to indicate the single bit of information 12 (e.g., logical state “1” or “0”). Two additional access transistors 18, 20 are provided to control access to the SRAM bitcell 10 during read and write operations. Access to the 6-T SRAM bitcell 10 is enabled by a wordline signal 22 asserted on a wordline 24 that controls the two (2) access transistors 18, 20. The assertion of the wordline signal 22 on the wordline 24 activates the two (2) access transistors 18, 20 causing the bitline 26 and the bitline complement 28 to be coupled to the two (2) cross-coupled inverters 14, 16. Thus, the bitline 26 and the bitline complement 28 are used to transfer data for both read and write operations.
As an example, in a read operation, activation of the access transistors 18, 20 causes the single bit of information 12 to be placed on the bitline 26 and the bitline complement 28 by the two (2) cross-coupled inverters 14, 16. The single bit of information 12 is placed on the bitline 26 and the bitline complement 28 in the form of voltage or current levels. A sense amplifier 30 detects the voltage differential between the bitline 26 and the bitline complement 28 indicating one of two logical states, as discussed above. In a write operation, an input driver 32 places a voltage 34 and a voltage complement 36 on the bitline 26 and the bitline complement 28, respectively. The voltage 34 and the voltage complement 36 placed on the bitline 26 and the bitline complement 28, respectively, by the input driver 32 represent the single bit of information 12 to be stored. Activation of the access transistors 18, 20 by the wordline 24 causes the voltage 34 and the voltage complement 36 on the bitline 26 and the bitline complement 28 to be stored or latched into the two (2) cross-coupled inverters 14, 16.
The bitline 26 and the bitline complement 28 in the 6-T SRAM bitcell 10 in FIG. 1 may be pre-charged by a bitline pre-charge signal 38 and a bitline pre-charge signal complement 40, respectively to a known, stable voltage level (i.e. logical high “1” or logical low “0”) prior to a read or write access. Pre-charging the bitline 26 and the bitline complement 28 allows the sense amplifier 30 to efficiently interpret differential voltage levels as a bit state, and allows the SRAM bitcell 10 to start from a known condition in order to prevent cell disturbances of the SRAM bitcell 10. The pre-charging of the bitline 26 and the bitline complement 28 is deactivated upon assertion of the wordline 24, thus allowing the initial known voltage level to be modified by the two (2) cross-coupled inverters 14, 16 or by the input driver 32, as described above in the read or write operations. After the read or write operation to the 6-T SRAM bitcell 10 has been completed for a memory access request, the bitline 26 and the bitline complement 28 can be pre-charged back to this known pre-charge voltage level to prepare for a next memory access request.
As discussed above, for SRAM designs that employ pre-charging of the bitlines of a SRAM bitcell column, a memory address in a memory access request can be used to identify a particular row or column of SRAM bitcells being accessed for pre-charging. The memory access request employs a memory access request circuit to translate the memory address in the memory access request to the particular row or column being accessed for pre-charging. However, providing this additional circuitry may add latency to the memory access request. To avoid this additional latency, SRAM designs may involve pre-charging all row or columns of the SRAM bitcells after the read or write operation has been completed to prepare the SRAM bitcells for the next memory access request. Thus, additional circuitry for translating the memory address in the memory access request to the particular row or column of SRAM bitcells is not necessary. However, maintaining a bitline pre-charge may increase leakage power during memory idle times when the SRAM bitcells are not being accessed.
Thus, SRAM designs that involve pre-charging all row or columns of the SRAM bitcells can consume more power than SRAM designs that identify the particular row or columns of the SRAM bitcells as part of the memory access request. However, SRAM designs that involve pre-charging all row or columns of the SRAM bitcells may not include additional latency from circuitry used to identify the particular row or column being accessed as part of the memory access request for pre-charging.